Metal-oxide semiconductor field effect transistor (MOSFET) devices are used in many integrated circuit designs, serving as switches to open and close the circuits. In general, a MOSFET device comprises a source region and a drain region connected by a channel, and a gate stack separated from the channel by a gate dielectric. The channel can comprise an n-type or p-type semiconductor material, forming an n-channel MOSFET (NMOSFET) or a p-channel MOSFET (PMOSFET) device, respectively.
Traditionally, the gate stack in a MOSFET device would comprise a semiconductor material, such as silicon, over a nitride-containing layer, which serves as the gate dielectric. Current research, however, is focused on the development of metal-gated MOSFET devices, e.g., MOSFET devices wherein the gate stack comprises a metal gate layer over a high-K layer, which serves as the gate dielectric. The use of metal-gated MOSFET devices is favorable for complementary metal-oxide semiconductor (CMOS) technology scaling. As such, with the current need for transistors having smaller feature sizes, improved metal-gated MOSFET devices are in demand.
To implement a metal gate stack in a MOSFET device, an interfacial oxide region is typically incorporated between the gate stack and the channel. However, regrowth of the interfacial oxide region, e.g., during fabrication of the device, can negatively affect device performance, as it increases the effective oxide thickness (EOT) and degrades the short channel and scaling benefits of the metal gate.
Typically, with metal-gated MOSFET devices, regrowth of the interfacial oxide region is prevented by amorphous silicon (Si) or poly-silicon (poly-Si) present in the gate stack over the metal gate layer which serves to attract background oxygen, and thereby prevents regrowth of the interfacial oxide region. However, to be effective at preventing regrowth the amorphous Si or poly-Si has to be located in close proximity to the interfacial oxide region. Since the metal gate layer is present in the gate stack between the amorphous Si/poly-Si and the interfacial oxide region, the thickness of the metal gate layer is limited, typically to about 10 nanometers. Having a thicker metal gate layer places the interfacial oxide region too far away from the amorphous Si/poly-Si and thus leads to regrowth of the interfacial oxide region. Having this thickness limitation is disadvantageous because increasing the thickness of the metal gate layer can enhance device performance.
Therefore, techniques that permit the metal gate layer thickness to be increased, and thus enhancing device performance, without causing regrowth at the interfacial oxide region would be desirable.